Digital circuits require a clock signal to operate. Typically, a clock signal is provided by a crystal oscillator and associated circuitry, which usually does not provide a clock signal having a duty cycle of 50%. For example, the clock signal may have a duty cycle of 45%, where the logic high phase of the clock signal is 45% of the clock cycle and the logic low phase of the clock signal is the remaining 55% of the clock cycle.
One type of circuit that requires a clock signal to operate is a memory circuit, such as a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR-SDRAM). For memory circuits operating at high frequencies, a clock signal having a duty cycle as close to 50% as possible is desired so that the memory has approximately an equal amount of time on both the logic high phase and logic low phase of the clock signal for transferring data. A duty cycle of 50% allows the maximum amount of time for latching both rising edge data and falling edge data in a memory circuit. To determine if the duty cycle of a clock signal is greater than 50%, less than 50%, or equal to 50%, a duty distortion detector is used.